【電機系書報討論演講訊息】

演講公告網址：/p/403-1175-2629-1.php

題   目： "從幾篇 ECO papers 一窺 formal verification 相關應用的研究" 

講   員：黃鐘揚 教授 (台大電子所)

時   間：2013年2月22日(星期五) 下午2時20分 (2時10分入場)

地   點：資電館206教室
 

Abstract:

People tend to think that "formal verification" is a hard topic with high

entrance barrier. Well, that is true if you want to be a hard-core formal

verification researcher. However, formal verification also gains its

popularity in various areas of applications, ranging from the conventional

hardware/software verification, to the hardware/software design

optimization, and even for the network security problems. In these

applications, only limited knowledge of formal verification is required. In

this talk, I will use some of our recent publications to illustrate how

formal verification techniques can be applied to the design rectification

problem, aka the automatic "Engineering Change Order (ECO)" process.

Hopefully these examples can convince you that it is possible to extend your

research methodology to the realm of formal verification.

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