【電機系書報討論演講訊息】

書報討論網址：http://www.ee.nthu.edu.tw/~ee591000/

演講公告網址：/p/403-1175-2629-1.php

題   目：Arms Race on Design Verification

講   員：Dr. Ying-Tsai Chang (RD Director, Springsoft USA)

時        間：2012年10月5日(星期五) 下午2時20分

地        點：資電館206教室
  

摘   要︰

Verification is of growing importance in modern chip development, generally considered

taking around 70% of product development effort. With the advances in language standard

and tool chain support, constraint random simulation methodology has been able to scale

for verification at IP level with proper planning. However, the design scale and test

environment complexity for SOC design poses significant challenges for simulation as a

practical verification paradigm. Hardware Assisted Verification (HAV) is increasingly

becoming the dominant practical SOC verification methodology for its order-of-magnitude

performance and capacity benefits. HAV encompasses a large range of solutions from

established custom circuit emulators to varieties of FPGA prototyping with various

degrees of customizations. By utilizing high capacity FPGA at the leading edge of

process node, FPGA prototyping is capable of effectively riding the Moore's law for long

term roadmap scalability. Leading SOC design companies invest significant resources

designing and building custom FPGA prototype systems.

State of the art FPGA prototype systems integrate tens of high capacity FPGA chips

across multiple high layer count PCB boards with complex high speed interconnection,

communication and clock scheme. Considering the scale and complexity of the design, the

advanced technologies used and the capital investment involved in their deployment, it

is effectively a dedicated computing machine arms race at the verification frontier. In

this talk, we review some of the key technologies in enabling FPGA prototype system for

effective design verification. 

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